Harvard Architecture

From http://www.wikipedia.org/wiki/Harvard_architecture ...

The term Harvard architecture originally referred to computer architectures that used physically separate storage devices for their instructions and data (in contrast to the VonNeumannArchitecture). The term originated from the Harvard Mark I relay based computer, which stored instructions on punched tape and data in relay latches.

The term Harvard architecture is usually used now to refer to a particular computer architecture design philosophy where physically separate data paths exist for the transfer of instructions and data.

From one point of view the VonNeumannArchitecture has "won" -- most memory (hard drives and RAM) can as easily hold data as instructions.

From another point of view the HarvardArchitecture is still going strong -- most desktop CPUs have an internal "instruction cache" feeding the control unit and a completely separate "data cache". When the executable code is modified, the cache must be flushed ...

Many DigitalSignalProcessors have three completely separate "data" paths -- one leading from the instruction memory (typically FLASH or EPROM), one from the coefficient memory (sometimes FLASH or EPROM, usually RAM), and one from the buffer memory (always RAM). That's the only way to get all three items in a single memory cycle. One popular DSP architecture is the SHARC architecture from Analog Devices; SHARC is short for "Super Harvard ARChitecture". (One suspects the name is intended to poke a bit of fun at the SPARC architecture...)

I once worked with a microcontroller (the Infineon C16x) that had five data paths: one from the flash, two for a small dual-ported RAM area (one read and one write), one for a larger RAM area, and one for internal peripherals. Any area could be used for instructions or data, but it was faster to use the flash for instructions and the others for data.


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