A second value of Bynase is that it encourages casual small-scale hardware/software projects. See the BynaseEcosystem for information about the amateur scientific exploration of biologically inspired design.
Bynase in a nutshell:
Bynase computers pull the capacitative load on a wire high or low for a few processor clock ticks and then disconnect for many many thousands of clocks before repeating the process. The exact number of clocks that pulling happens is determined based on the strength of the the particular pin drivers and can vary with variation in electrical design.
Bynase does not use any passive pull-ups or pull-downs. The Atmel AVR designs have internal pull-ups that must be disabled.
Computers drive pulses without regard to anything else happening on the wire. Pulse frequency is roughly equivalent to the NTSC horizontal sweep rate of 15kHz. Higher rates make for a more dominant signal when multiple computers are driving the same net.
Values are driven onto a net by choosing proportionally high or low drive for subsequent pulses. Conceptually this is as simple as:
while true if value < random pulse low else pulse highNote: this is not a positional number system where subsequent bits represent progressively larger (or smaller) weight. Every pulse sent is equally likely to influence a receiver by the same amount.
A receiver samples the signal on a net and accumulates a progressively better estimate of the value present. For example, 100 samples can yield an accumulation between 0 and 100 inclusively.
result = 0 for 100 times if input is high result = result + 1A receiver does not know which transmitter has most recently pulsed the net. As such, when multiple transmitters compete, the receiver detects a weighted average of the transmitted signal.
The Bynase driver delays sampling input until the last possible moment before pulsing its own signal and thus obliterating any other computer's signal. This strategy allows two computers to signal each other on a single wire. Crosstalk will be minimized when the two computers signal at the same rate.
A receiver integrates both the signal and the statistical "noise" used to carry it. We choose to use "noise" that has no frequency components with periods longer than typical integration periods. In this way most noise cancels out in the receiver's integrator. The Bynase driver uses an InvertedCounter as a high-frequency noise generator.
An alternative would be to use an ErrorDiffusion process in place of what is essentially a static dither. This is the approach used by PulseDensityModulation used by, so called, one-bit D-to-A converters in high end compact disk players.
In the limit, probability 0 => always low and probability 1 => always high. We achieve these limits by slightly reducing the range of the inverted counter. Specifically we skip zero so an 8-bit counter has only 255, not 256, states, and that value < random evaluates to produce pulse low for all values of random when value is zero.
We have considered alternative methods to reconstruction other than linear integration. One study, FastBynase, produced some simulations that inform all versions of Bynase with some very clear pictures.
In this one, the first trace (red) is the signal to be encoded, the second (blue) is the noise from the InvertedCounter used to dither the signal, and, the third (green) is the signal as it might appear on the wire if there were no other signals present. The remaining waveforms are specific to the FastBynase reconstruction.
Bynase takes inspiration from molecular signaling systems where concentrations encode values. While Bynase is not particularly good at signaling high-speed events, Bynase designs tend to be immune to occasional and short-lived errors. Bynase systems have the feel of hybrid computers (mixed analog and digital) except that the digital component is distributed among all of the "analog" elements.
|Last edited March 30, 2008
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